LOW POWER KA-BAND DIRECT CONVERSION RECEIVER MODULE (ARTES AT 5C.525) - EXPRO+ (ON DELEGATION REQUEST)

The objective: The objective of the activity is to design, manufacture and test a 12bit direct conversion receiver module covering the full Ka-band with significant reduced power consumption in comparison to current state of the art.Targeted Improvements:- Enabling a European source of low power direct conversion Ka-band receivers.- Factor 5 reduction of power consumption compared to the State of the Art.Description: Today's flexible telecommunication satellites require receivers operating at higher frequencies and over a wider bandwidth than in the past, with a complex RF chain and lossyharnesses. A trend towards highly integrated solutions using direct sampling receivers compatible with Software Defined Radios (SDRs) is one solution, but the power consumption of these direct sampling architectures can be prohibitive for some applications. The available direct conversion receivers in Ku-band and Ka-band have power consumption figuresin excess of several Watts and limited conversion accuracy, constraining the application areas where these could be used for space telecommunication applications. A direct conversion receiver system in a single package integrating the Analog to Digital Converter (ADC) in the advanced semiconductor technology and using a time-interleaved ADCarchitecture can achieve the desired lower power consumption and higher conversion accuracy.This activity will develop a prototype wideband ADC with high-speed track-and-hold circuit, implemented as a System-in-Package (SiP) RF to digital front-end module including digital processing features, operating in upper Ka-band. Available State-of-the-Art low-power wideband ADC will be assessed, and a trade-off analysisperformed to determine the optimum RF chain architecture (including the track-and-hold with digital processing engine and high-speed interfaces) suitable for wideband SDRs operating in full Ka-bandapplications. The breadboard will be designed to meet key performance requirements in terms of power consumption (<500mW per channel), bandwidth, and input frequency. The noise and linearity performance shall be measured to determine suitability for a range of SDR scenarios also considering synchronisation and clock jitter requirements. The breadboard shall be tested in a representative RF chain architecture in a laboratory environment, to demonstrate direct sampling at upper Ka-band frequencies and assess viability for V/W band applications. Additionally, radiation tolerance shall be demonstrated by analysis to assess suitability of the low-power ADC for future applications in space.